- Ms. TEJASWINI H
- Dr. DEEPIKA B.V
- Dr. SHRIVATHSA T V
- Mr. SUNIL S HALDANKAR
“COSMOS-RV: A Lightweight Single-Issue Speculative Out-of-Order 32-bit RISC-V Processor With Virtually Indexed Physically Tagged Cache Architecture and FPGA Validation”
https://ieeexplore.ieee.org/document/11540152
- Mr. BALACHANDRA R JOGI
“An Efficient Vedic Multipliers Implementation Using Precomputation Logic”
- Mr. SARVESH S RAO