Workshop on Verilog Programming

Shri Madhwa Vadiraja Institute of Technology & Management, Bantakal, in association with ISTE Student Chapter and Contemporary Verification Consultants (CVC) Pvt. Ltd., a top notch VLSI design Verification Company based in Bengaluru, organized a 5-day Workshop on Verilog Programming for the benefit of final and pre-final year students of Electronics & Communication Engineering branch, from 19 to 23 January 2016. Mr. Nagasundaram, Mr. B Srinivas and Mr. Sachin, of CVC Pvt. Ltd. were the resource persons. More than 50 students of the college participated in the workshop and enriched their knowledge on the advancements in VLSI and Verilog.

During the workshop, the resource persons highlighted on the ASIC flow design and briefed about the levels of abstraction, anatomy of Verilog, operators, procedural blocks and loop constructs, focusing on different modeling techniques used in Verilog. Students were made to concentrate on gate level modeling along with timing specifications and verification perspective. They were made aware about the Verilog-2001 enhancements, case constructs tasks and functions. They were trained to write Verilog code (DUT and Testbench) on their own for designing digital circuits. The students were motivated how to get industry ready and excel in the field of VLSI. The entire knowledge sharing and hands-on lab session benefited the students in understanding the concepts of Hardware Description Language and design of digital circuits using Modelsim tool.

During the inauguration session on the first day of the workshop, Prof. Dr. Thirumaleshwara Bhat, Principal of SMVITM, congratulated the department of ECE for holding such important training program for the benefit of students during their vacation. Dr. A. Ganesha, Dean (Academics), Prof. Dr. Balachandra Achar, HOD of ECE department, and the faculty members of ECE department were present during the occasion. Earlier, Ms. Sowmya Bhat, Asst. Professor, gave a brief prelude to CVC, Verilog and welcomed the gathering. Mr. Nagasundaram of CVC Pvt. Ltd., briefed about CVC and the importance of HDL and Verilog. Mr. Raghavendra Rao P, Asst. Professor, proposed the vote of thanks and Ms. Anusha Pai compered the program, which was coordinated by the volunteers of ISTE Student Chapter.