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DR. RASHMI SAMANTH

Assistant Professor (sg)
    Artificial Intelligence and Machine Learning
    rashmi.ml@sode-edu.in
    • P. hD. (VLSI)
    • M. Tech. (VLSI Design)
    • B. E. (Electronics and Communication Engineering)
    Low Power VLSI
    2 Years 5 Months
    • VLSI
    • Low Power VLSI

    • Samanth, R. and Nayak, S.G., 2022. An Efficient Two-phase Clocked Sequential Multiply-Accumulator Unit for Image Blurring. International Journal of Electronics and Telecommunications, 68. S, 2022, VOL. 68, NO. 2, PP. 307-313. DOI:10.24425/ijet.2022.139883((Impact Factor: 0.92) (Q3)
    • Samanth, R., Nayak, S.G., “Design and SV based verification of AMBA AXI protocol for SOC integration,” in International Journal of Recent Technology and Engineering, Vol 8(2), pp.1465-1469, July 2019, Doi: 10.35940/ijrte.B2110.078219,(Impact Factor: 0.107) (Q4).
    • Samanth, R., Kedlaya K, V., Nayak, S.G. “A Novel Approach to Develop Low Power MACs for 2D Image Filtering,” IEEE Access, vol. 9, pp. 28421-28428, 2021. DOI:10.1109/ACCESS.2021.3058736, (Scopus Indexed/ web of science) (Impact Factor: 3.367) (Q1).
    • Samanth, R., Nayak, S.G., “An Efficient Two-phase Clocked Sequential Multiply -Accumulator unit for Image blurring”, International Journal of Electronics and Telecommunications, (Accepted). (Scopus Indexed/ web of science) (Impact Factor: 0.93) (Q3). (Awaiting publication vol.2, 2022). (Q3).
    • Kaushik, M.K., R Samanth, R., Nayak, S.G., “Modified illumination invariant algorithm based human face detection”, International Journal of Scientific and Technology Research, 2020, 9(4), pp. 592–595 (Scopus Indexed).
    • Samanth, R., Nayak, S.G., and Nempu, P.B., “A Novel Multiply-Accumulator Unit Bus Encoding Architecture for Image Processing Applications”, Iranian Journal of Electrical and Electronic Engineering, 19(1).
    • Abhishek S Tantry, Jeevan S, Mohammed Zain, Prajwal, Rashmi Samanth “Design and Development of IoT Based Smart Dairy Farming”, GIS Science Journal, Volome 10, ISSUE 5, 2023, PAGE NO:1441, ISSN NO: 1869-9391
    • Abhishek S Tantry, Jeevan S, Mohammed Zain, Prajwal, Rashmi Samanth, “Development of Smart Dairy Farming”, International Journal of Advanced Research in Computer and Communication Engineering”, ISSN(o): 2278-1021 ISSN (P), 2319-5940.

    • Presented the research paper entitled “Design and Analysis of Four Port Router for Network-On-Chip Applications” in the Second International Conference on Artificial Intelligence, Computational Electronics and Communication System (AICECS 2023), organized by the Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal.
    • Presented the research paper entitled “Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors” in the Second International Conference on Artificial Intelligence, Computational Electronics and Communication System (AICECS 2023), organized by the Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal.
    • Samanth, R., Chaitanya, C.V.S., Nayak, G.S., “Power Reduction of a Functional unit using RT-Level Clock-Gating and Operand Isolation”, 2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Manipal, India, 2019, pp. 1-4, DOI: 10.1109/DISCOVER47552.2019.9008025.
    • Samanth, R., Amin, A., Nayak, S.G., “Design and Implementation of 32-bit Functional Unit for RISC architecture applications”, 2020 IEEE 5th International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, 2020, pp.46-48, DOI:10.1109/ICDCS48716.2020.243545. 28
    • Samanth, R., S., P., Nayak, S.G., “High-Speed Hybrid Tree Multiplier Hardware using modified Wallace and Dadda Method”, AIP Conference Proceedings, vol. 2358, no.1, p. 080014. AIP Conference Proceedings LLC, 2021.
    • Samanth, R., Joshi, S.S., Nayak, S.G., “Design and Implementation of High-Performance Hybrid Adders”, AIP Conference Proceedings, vol. 2357, no.1, p. 020003. AIP Publishing LLC, 2022.
    • Sahu, A.K., Samanth, R., Mendez, T., Nayak, S.G., Kedlaya, K.V., “VLSI design techniques for low power MAC unit: A review”, AIP Conference Proceedings, vol.2358, No. 1, p. 050013. AIP Publishing LLC, Jul 30, 2021.

    • Participated in One week International Faculty Development Program on “NLP and ChatGPT Applications” organized by SECAB Institute of Engineering and Technology from 14/08/2023 to 19/08/2023.
    • Participated in the AICTE Recognized Faculty Development Programme on “Protection from Cyber Attacks” Conducted by Information Management and Emerging Engineering Department from 07/08/2023 to 11/08/2023 (One Week) at NITTTR, Chandigarh.
    • Participated in Faculty Development Workshop on “VLSI to System Design: Silicon-to-End Application Approach” from 31/07/2023 to 04/08/2023 conducted by AICTE in association with ARM Education and ST Microelectronics with support from Cadence Design Systems.
    • Participated in One-week Faculty Development Program on “Artificial Intelligence and its Applications”, conducted by Department of Computer Science and Engineering from 03/07/2023 to 08/07/2023 at Chalapathi Institute of Technology.
    • Participated in Three days Faculty Development Program on “Curriculum Design” organized by Internal Quality Assurance Cell, Mangalore Institute of Engineering & Technology from 22/05/2023 to 24/05/2023.
    • Participated in Two days workshop on “Digital Analog and Mixed Signal Modelling and Verification with the State of the Art EDA Tools”, held on 10/03/2023 to 11/03/2023 at Manipal School of Information Sciences, MAHE, Manipal.
    Asst. Professor (SG)
    Department of AI-ML Engineering
    Shri Madhwa Vadiraja Institute of Technology and Management
    Vishwothama Nagar, Bantakal
    Udupi – 574 115
    Karnataka, India.
    1-24041491882

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