One Day workshop on RTL TO GDSII: Explore VLSI using open-source tools

The Department of Electronics and Communication Engineering, in collaboration with the ISTE Student Chapter and IIIC, successfully organized a workshop for third and fourth-year ECE students on 08 November 2025. The event was conducted in the DSP Lab of the Electronics and Communication Engineering Department, with Mr. N. J. Hariprasad, Anamaya Technologies, Udupi, serving as the resource person.

The session began with a welcome address by Mr. Arun Upadyaya, Head of the Department, Electronics and Communication Engineering. A hands-on session on Open-Source Tools for VLSI was conducted to provide practical exposure to various stages of the VLSI design flow using freely available software. The workshop started with an introduction to basic Linux commands, which are essential for operating open-source Electronic Design Automation (EDA) tools efficiently.

Following this, participants designed a Multiplexer (MUX) module using Verilog HDL and developed a corresponding testbench to verify its functionality. The simulation was performed using Icarus Verilog, and the output waveforms were viewed using GTKWave, which helped participants understand signal behavior and timing analysis.

In the next part of the workshop, the schematic of a CMOS inverter was created using Xschem. This schematic was then used to design the layout in Magic, enabling students to gain practical experience in layout design, understand different layers, and learn how circuit connectivity is translated into physical structure on silicon.

The workshop also included a discussion on Static Timing Analysis (STA) using OpenSTA, where key concepts such as setup time, hold time, clock constraints and timing verification were explained. This session helped participants understand the importance of timing in ensuring the correct operation of digital circuits.

Overall, the workshop provided a complete overview of the VLSI design flow using open-source tools, covering coding and simulation, schematic design, layout development and timing verification. The session was highly informative and helped bridge the gap between theoretical learning and practical application in integrated circuit design.

At the end of the session, Mr. Arun Upadyaya presented a letter of appreciation to Mr. N. J. Hariprasad. The event was efficiently coordinated by Ms. Chandana, ISTE Department Coordinator, with support from Mr. Chetan R., Department Coordinator, IIIC.