{"id":40875,"date":"2025-10-31T20:09:06","date_gmt":"2025-10-31T20:09:06","guid":{"rendered":"https:\/\/sode-edu.in\/smvitm\/?p=40875"},"modified":"2026-01-14T20:10:47","modified_gmt":"2026-01-14T20:10:47","slug":"two-day-workshop-on-logic-to-layout-vlsi-design-essentials-30-31-october-2025","status":"publish","type":"post","link":"https:\/\/sode-edu.in\/smvitm\/news-2\/news\/two-day-workshop-on-logic-to-layout-vlsi-design-essentials-30-31-october-2025\/","title":{"rendered":"Two-Day Workshop on \u201cLogic to Layout \u2013 VLSI Design Essentials\u201d | 30\u201331 October 2025"},"content":{"rendered":"

\"\"A two-day hands-on workshop on \u201cLogic to Layout \u2013 VLSI Design Essentials\u201d was organized by the Department of Electronics and Communication Engineering, in association with IEEE ComSoc and the Co-curricular Cell, on 30 and 31 October 2025. The workshop commenced with a formal inauguration on 30 October 2025 at 9:30 AM, in the presence of the Head of the Department and the invited resource persons Mr. Sujay Kumar and Mr. Sandesh Kumar. The inauguration was compered by Ms. Poornitha, and the resource persons were welcomed with floral gestures by Mr. Sachin Prabhu K. and Mr. Sandeepa Prabhu (Department Co-curricular Cell Coordinator). The workshop was supported by trainers Mr. Vijeth Rai and Mr. Sanketh C. Naik, who assisted throughout the sessions.<\/p>\n

The technical sessions provided participants with practical exposure to VLSI physical design using the Cadence design tool. Students extracted a PMOS device from the standard library and designed it from scratch as per specified dimensions, followed by Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification to obtain an error-free layout. In the afternoon session, participants designed an inverter circuit by completing both schematic and layout, followed by DRC and LVS checks. On the second day, students worked on the schematic and layout design of a Level Shifter circuit, gaining deeper understanding of layout implementation and verification processes. The resource persons and trainers also explained common DRC errors, their causes, and solutions, while highlighting essential layout design rules such as minimum spacing requirements.<\/p>\n

The workshop was highly informative, interactive, and application-oriented, offering real-time exposure to industry-standard EDA tools and strengthening students\u2019 foundational and practical knowledge in VLSI design. The programme concluded with a valedictory session on 31 October 2025 at 4:30 PM, where the Department IEEE Coordinator Dr. Shilpa Kamath S. delivered the valedictory address and expressed gratitude to the resource persons, trainers, organising team, and participants for the successful completion of the workshop.<\/p>\n","protected":false},"excerpt":{"rendered":"

A two-day hands-on workshop on \u201cLogic to Layout \u2013 VLSI Design Essentials\u201d was organized by the Department of Electronics and Communication Engineering, in association with IEEE ComSoc and the Co-curricular Cell, on 30 and 31 October 2025. The workshop commenced with a formal inauguration on 30 October 2025 at 9:30 AM, in the presence of<\/p>\n","protected":false},"author":1,"featured_media":40876,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[263,83,58,259,33],"tags":[],"class_list":["post-40875","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-co-curricular-news","category-ec-news","category-gallery","category-ieee-news","category-news"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t