{"id":40819,"date":"2026-01-10T17:52:41","date_gmt":"2026-01-10T17:52:41","guid":{"rendered":"https:\/\/sode-edu.in\/smvitm\/?p=40819"},"modified":"2026-01-14T17:54:49","modified_gmt":"2026-01-14T17:54:49","slug":"one-day-fdp-on-open-source-rtl-to-gds-design-flow","status":"publish","type":"post","link":"https:\/\/sode-edu.in\/smvitm\/news-2\/news\/one-day-fdp-on-open-source-rtl-to-gds-design-flow\/","title":{"rendered":"One-Day FDP on Open-Source RTL to GDS Design Flow"},"content":{"rendered":"

\"\"Department of Electronics and Communication Engineering, successfully organized a One-Day Faculty Development Programme (FDP) titled \u201cRTL to GDS: Open-Source Design Flow for FPGA and VLSI Systems\u201d on 10 January 2026 at the CAED Lab of the institute.<\/p>\n

The programme was organized in association with Anmaya Technologies, Udupi, the Industry Institute Interaction Cell (IIIC), and the ISTE Faculty Chapter, with the objective of imparting hands-on training on the complete open-source chip design flow using modern Electronic Design Automation (EDA) tools.<\/p>\n

The programme was convened by Mr. Arun Upadhyaya, HoD, Department of Electronics and Communication Engineering, and coordinated by Mr. Chetan R, Assistant Professor (SG), Department of ECE, with the support of organizing committee members Ms. Chandana, Assistant Professor, and Ms. Akshatha Rao L, Assistant Professor (Senior), Department of ECE.<\/p>\n

The FDP was conducted by the resource persons Mr. N. J. Hariprasad and Mr. Tushar Shenoy from Anmaya Technologies, Udupi, who delivered expert sessions covering the complete RTL-to-GDS design flow using open-source tools. The programme included hands-on sessions on functional simulation using Icarus Verilog and GTKWave, logic synthesis using Yosys, gate-level simulation, static timing analysis, and digital flow integration using OpenLane.<\/p>\n

The FDP enabled participants to understand and practice the integration of various open-source tools into a complete digital design flow, making advanced VLSI education and research accessible without reliance on expensive proprietary software. The programme was well received by faculty members, researchers, and professionals, who appreciated the practical exposure and industry relevance of the sessions.<\/p>\n

The event concluded with positive feedback from participants, highlighting the effectiveness of the FDP in enhancing technical skills and fostering industry-oriented learning in the field of VLSI and FPGA design.<\/p>\n","protected":false},"excerpt":{"rendered":"

Department of Electronics and Communication Engineering, successfully organized a One-Day Faculty Development Programme (FDP) titled \u201cRTL to GDS: Open-Source Design Flow for FPGA and VLSI Systems\u201d on 10 January 2026 at the CAED Lab of the institute. The programme was organized in association with Anmaya Technologies, Udupi, the Industry Institute Interaction Cell (IIIC), and the<\/p>\n","protected":false},"author":1,"featured_media":40820,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[83,58,128,33],"tags":[],"class_list":["post-40819","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ec-news","category-gallery","category-iste-news","category-news"],"acf":[],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t